IS61WV5128ALL Datasheet, PDF (12/25 Pages) Integrated Silicon Solution, Inc – 512K x 8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol
twc
tsce
taw

tha
tsa
tpwe1
tpwe2
tsd
thd
thzwe⁽²⁾
tlzwe⁽²⁾
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-8
Min. Max.
8
—
6.5 —
6.5 —
0
—
0
—
6.5 —
8.0 —
5
—
0
—
— 3.5
2
—
-10
Min. Max. Unit
10 —
ns
8
—
ns
8
—
ns
0
—
ns
0
—
ns
8
—
ns
10 —
ns
6
—
ns
0
— ­ns
—
5
ns
2
—
ns
Notes:
1.  Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output load-
ing specified in Figure 1.
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one
can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that
terminates the write. Shaded area product in development
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  I
08/10/09