IS61WV5128ALL Datasheet, PDF (10/25 Pages) Integrated Silicon Solution, Inc – 512K x 8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)

Symbol

Parameter
-20 ns -25 ns
Min. Max.
Min. Max.
-35 ns
Min. Max.
Unit
trc
Read Cycle Time
20 —
25 —
35 —
ns
taa
Address Access Time
— 20
— 25
— 35
ns
toha
Output Hold Time
2.5 —
4 —
4 —
ns
tace
CE Access Time
— 20
— 25
— 35
ns
tdoe
OE Access Time
— 8
— 12
— 15
ns
thzoe⁽²⁾
OE to High-Z Output
0 8
0 8
0 10
ns
tlzoe⁽²⁾
OE to Low-Z Output
0 —
0 —
0 —
ns
thzce⁽²
CE to High-Z Output
0 8
0 8
0 10
ns
tlzce⁽²⁾
CE to Low-Z Output
3 —
10 —
10 —
ns
tpu
Power Up Time
0 —
0 —
0 —
ns
tpd
Power Down Time
— 20
— 25
— 35
ns
Notes:
1.  Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vdd-0.3V and output loading specified in Figure 1a.
2.  Tested with the load in Figure 1b.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  Not 100% tested.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  I
08/10/09