IS61WV5128ALL Datasheet, PDF (13/25 Pages) Integrated Silicon Solution, Inc – 512K x 8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)

Symbol
-20 ns -25 ns -35 ns
Parameter Min. Max.
Min. Max.
Min. Max. Unit
twc
tsce
taw

Write Cycle Time
CE to Write End
Address Setup Time
to Write End
20 —
12 —
12 —
25 —
18 —
15 —
35 —
ns
25 —
ns
25 —
ns
tha
tsa
tpwe1
tpwe2
tsd
thd
thzwe⁽³⁾
tlzwe⁽³⁾
Address Hold from Write End
Address Setup Time
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0 —
0 —
12 —
17 —
9 —
0 —
— 9
3 —
0 —
0 —
ns
0 —
0 —
ns
18 —
30 —
ns
20 —
30 —
ns
12 —
15 —
ns
0 — ­0 —
ns
— 12
— 20
ns
5 —
5 —
ns
Notes:
1.  Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse
levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a.
2.  Tested with the load in Figure 1b.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev.  I
08/10/09