IS61WV3216DALL Datasheet, PDF (9/20 Pages) Integrated Silicon Solution, Inc – 32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)

-8
-10
-12
1
Symbol Parameter Min. Max.
Min. Max. Min. Max.
Unit
trc
Read Cycle Time
8—
10 —
12 —
ns
taa
Address Access Time
toha
Output Hold Time
—8
2.0 —
— 10
2.0 —
— 12
ns
3—
ns
2
tace
CE Access Time
—8
— 10
— 12
ns
tdoe
thzoe⁽²⁾
tlzoe⁽²⁾
OE Access Time
OE to High-Z Output
OE to Low-Z Output
— 5.5
—3
0—
— 6.5
—4
0—
— 6.5
ns
—6
ns
3
0—
ns
thzce⁽²
CE to High-Z Output
03
04
06
ns
tlzce⁽²⁾
tba
CE to Low-Z Output
LB, UB Access Time
3—
— 5.5
3—
— 6.5
3—
ns
— 6.5
ns
4
thzb⁽²⁾
LB, UB to High-Z Output
0 5.5
0 6.5
0 6.5
ns
tlzb⁽²⁾
tpu
tpd
LB, UB to Low-Z Output
Power Up Time
Power Down Time
0—
0—
—8
0—
0—
— 10
0—
ns
0—
ns
5
— 10
ns
Notes:
1.  Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage.
6
7
8
9
10
11
12
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. A
05/14/2012