IS61WV3216DALL Datasheet, PDF (15/20 Pages) Integrated Silicon Solution, Inc – 32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
AC WAVEFORMS
1
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) ⁽¹⁾
t WC
2
ADDRESS
VALID ADDRESS
OE LOW
CE _LOW
t HA
3
t AW
t PWE2
WE
t SA
t PWB
4
UB, LB
t HZWE
t LZWE
HIGH-Z
DOUT
DATA UNDEFINED
t SD
t HD
5
DIN
DATAIN VALID
UB_CEWR3.eps
6
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) ^(1,3)
7
t WC
t WC
ADDRESS
ADDRESS 1
ADDRESS 2
8
OE
CE _LOW
t SA
WE
UB, LB
DOUT
DIN
t PWB
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t HA
t SA
t PWB
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
9
10
11
Notes:
1.  Theinternal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in
valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced
to the rising or falling edge of the signal that terminates the Write.
2.  Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3.  WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
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Integrated Silicon Solution, Inc. — www.issi.com
15
Rev. A
05/14/2012