IS61WV3216DALL Datasheet, PDF (10/20 Pages) Integrated Silicon Solution, Inc – 32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)

-20 ns -25 ns
Symbol Parameter Min. Max.
Min. Max.
-35 ns -45 ns
Min. Max.
Min. Max.
Unit
trc
Read Cycle Time
20 —
25 —
35 —
45 —
ns
taa
Address Access Time
— 20
— 25
— 35
— 45
ns
toha
Output Hold Time
2.5 —
6—
8—
10 —
ns
tace
CE Access Time
— 20
— 25
— 35
— 45
ns
tdoe
OE Access Time
—8
— 12
— 15
— 20
ns
thzoe⁽²⁾ OE to High-Z Output
08
08
0 10
0 15
ns
tlzoe⁽²⁾ OE to Low-Z Output
0—
0—
0—
0
—
ns
thzce⁽² CE to High-Z Output
08
08
0 10
0 15
ns
tlzce⁽²⁾ CE to Low-Z Output
3—
10 —
10 —
10 —
ns
tba
LB, UB Access Time
—8
— 25
— 35
— 45
ns
thzb
LB, UB to High-Z Output
08
08
0 10
0 15
ns
tlzb
LB, UB to Low-Z Output
0—
0—
0—
0
—
ns
Notes:
1.  Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vdd-0.3V and output loading specified in Figure 1a.
2.  Tested with the load in Figure 1b.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  Not 100% tested.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
05/14/2012