IS61WV3216DALL Datasheet, PDF (13/20 Pages) Integrated Silicon Solution, Inc – 32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM

IS61WV3216DALL/DALS, IS61WV3216DBLL/DBLS,
IS64WV3216DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)

-20 ns -25 ns -35 ns -45ns
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Symbol Parameter Min. Max.
Min. Max.
Min. Max.
Min. Max. Unit
twc
Write Cycle Time
tsce
CE to Write End
taw
Address Setup Time
to Write End
20 —
12 —
12 —
25 —
18 —
15 —
35 —
25 —
25 —
45 —
35 —
35 —
ns
2 ^ns
ns
tha
Address Hold from Write End 0 —
tsa
Address Setup Time
0—
tpwb
LB, UB Valid to End of Write
12 —
tpwe1 WE Pulse Width (OE = HIGH) 12 —
tpwe2 WE Pulse Width (OE = LOW) 17 —
tsd
Data Setup to Write End
9—
thd
Data Hold from Write End
0—
thzwe⁽³⁾ WE LOW to High-Z Output
—9
tlzwe⁽³⁾ WE HIGH to Low-Z Output
3—
0—
0—
18 —
18 —
20 —
12 —
0—
— 12
5—
0—
0—
30 —
30 —
30 —
15 —
­0 —
— 20
5—
0—
0—
35 —
35 —
35 —
20 —
0—
— 20
5—
ns
3 ^ns
ns
ns
4 ^ns
ns
ns
5 ^ns
ns
Notes:
1.  Test conditions for IS61WV3216LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse
levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a.
2.  Tested with the load in Figure 1b.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW.All signals must be in valid states to
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initiate a Write, but any one can go inactive to terminate the Write.The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
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Integrated Silicon Solution, Inc. — www.issi.com
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Rev. A
05/14/2012