IS61LPS51236B Datasheet, PDF (9/33 Pages) Integrated Silicon Solution, Inc – Internal self-timed write cycle

IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
TRUTH TABLE
SYNCHRONOUS TRUTH TABLE
OPERATION
ADDRESS /CE /CE2 CE2 ZZ /ADSP /ADSC /ADV /WRITE /OE CLK DQ
Deselect Cycle, Power-Down None
H
X
X
L
X
L
X
X
X L-H High-Z
Deselect Cycle, Power-Down None
L
X
L
L
L
X
X
X
X L-H High-Z
Deselect Cycle, Power-Down None
L
H
X
L
L
X
X
X
X L-H High-Z
Deselect Cycle, Power-Down None
L
X
L
L
H
L
X
X
X L-H High-Z
Deselect Cycle, Power-Down None
L
H
X
L
H
L
X
X
X L-H High-Z
Snooze Mode, Power-Down
None
X
X
X
H
X
X
X
X
X
X High-Z
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H L-H High-Z
Write Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X L-H
D
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H L-H High-Z
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H L-H High-Z
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H L-H High-Z
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X L-H
D
Read Cycle, Suspend Burst Current
X
X
X
L
H
H
H
H
L L-H
Q
Read Cycle, Suspend Burst Current
X
X
X
L
H
H
H
H
H L-H High-Z
Read Cycle, Suspend Burst Current
H
X
X
L
X
H
H
H
L L-H
Q
Read Cycle, Suspend Burst Current
H
X
X
L
X
H
H
H
H L-H High-Z
Write Cycle, Suspend Burst Current
X
X
X
L
H
H
H
L
X L-H
D
Write Cycle, Suspend Burst Current
H
X
X
L
X
H
H
L
X L-H
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (/BWa-d) and /BWE are LOW or /GW is LOW. /WRITE = H for all /BWx, /BWE, /GW HIGH.
3. /BWa enables WRITEs to DQa’s and DQPa. /BWb enables WRITEs to DQb’s and DQPb. /BWc enables WRITEs to DQc’s and DQPc. /BWd enables
WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except /OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, /OE must be HIGH before the input data setup time and held HIGH during the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. /ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and
/BWE LOW or /GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
Integrated Silicon Solution, Inc.- www.issi.com
9
Rev. B
10/16/2014