IS61LPS51236B Datasheet, PDF (10/33 Pages) Integrated Silicon Solution, Inc – Internal self-timed write cycle

IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
PARTIAL TRUTH TABLE
Operation
/GW
/BWE
/BWa
/BWb
READ
H
H
X
X
READ
H
L
H
H
WRITE BYTE a
H
L
L
H
WRITE BYTE b
H
L
H
L
WRITE BYTE c
H
L
H
H
WRITE BYTE d
H
L
H
H
WRITE ALL BYTEs
H
L
L
L
WRITE ALL BYTEs
L
X
X
X
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
ADDRESS SEQUENCE IN BURST MODE
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
LINEAR BURST ADDRESS TABLE (MODE = Vss )
0,0
/BWc
X
H
H
H
L
H
L
X
/BWd
X
H
H
H
H
L
L
X
3rd Burst Address
A1 A0
11
10
01
00
A1', A0' = 1,1
0,1
1,0
Power Up Sequence
VDDQ → VDD1 → I/O Pins²
Notes:
1. VDD can be applied at the same time as VDDQ
2. Applying I/O inputs is recommended after VDDQ is stable. The inputs of the I/O pins can be applied at the same time as VDDQ as long as Vih (level of
I/O pins) is lower than VDDQ.
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
Integrated Silicon Solution, Inc.- www.issi.com
10
Rev. B
10/16/2014