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IS61LPS51236B Datasheet, PDF (4/33 Pages) Integrated Silicon Solution, Inc – Internal self-timed write cycle
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IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
1024K x 18, 165-Ball BGA (Top View)
1
2
A NC
A
B NC
A
C NC NC
D NC DQb
E NC DQb
F NC DQb
G NC DQb
H NC
VSS
J DQb NC
K DQb NC
L DQb NC
M DQb NC
N DQPb NC
P NC NC
R MODE NC
3
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
4
/BWb
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
NC
/BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
A1*
A0*
7
/BWE
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
/ADSC
/OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
/ADV
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
165-Ball, 13 mm x 15mm BGA
PIN DESCRIPTION
Symbol
CLK
A0,A1
A
/ADV
/ADSP
/ADSC
MODE
CE, /CE, CE2
/BWE
/BWx (x=a-b)
/GW
/OE
DQx
TCK,TDI,
TDO,TMS
ZZ
NC
VDD
VDDQ
VSS
Pin Name
Synchronous Clock
Synchronous Burst Address Inputs
Address Inputs
Synchronous Burst Address Advance
Address Status Processor
Address Status Controller
Burst Sequence Selection
Synchronous Chip Enable
Byte Write Enable
Synchronous Byte Write Inputs
Global Write Enable
Output Enable
Data Inputs/Outputs
JTAG Pins
Power Sleep Mode
No Connect
Power Supply
I/O Power Supply
Ground
Integrated Silicon Solution, Inc.- www.issi.com
4
Rev. B
10/16/2014
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