IS61LPS51236B Datasheet, PDF (24/33 Pages) Integrated Silicon Solution, Inc – Internal self-timed write cycle

IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
Instruction Set
Code
000
001
010
011
100
101
110
111
Instruction
EXTEST
IDCODE
SAMPLE-Z
RESERVED
SAMPLE(/PRELOAD)
RESERVED
RESERVED
BYPASS
TDO Output
Boundary Scan Register
32-bit Identification Register
Boundary Scan Register
Do Not Use
Boundary Scan Register
Do Not Use
Do Not Use
Bypass Register
Notes
2, 6
1, 2
5
4
5
5
3
Notes:
1. Places DQs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to V_SS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the
shift-DR state.
4. SAMPLE instruction does not place DQs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6. By default, it places DQs in high-Z. If the internal register on the scan chain is set high, DQs will be updated with information loaded via a previous
SAMPLE instruction. The actual transfer occurs during the update IR state after EXTEST is loaded. The value of the internal register can be changed
during SAMPLE and EXTEST only.
ID Register Definition
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
Device Width (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
ID Register Presence (0)
Description
Reserved for version number.
Defines depth of SRAM. 512K or 1024K
Defines Width of the SRAM. x36 or x18
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
512K x 36
xxxx
00111
00100
xxxxxx
00001010101
1
1024K x 18
xxxx
01000
00011
xxxxxx
00001010101
1
Integrated Silicon Solution, Inc.- www.issi.com
24
Rev. B
10/16/2014