IS61LPS51236B Datasheet, PDF (20/33 Pages) Integrated Silicon Solution, Inc – Internal self-timed write cycle

IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
1. Instruction Register
This register is loaded during the update-IR state of the TAP controller. At power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a
reset state as described in the previous section. When the TAP controller is in the capture-IR state, the two LSBs
are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.
2. Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to
be shifted through the SRAM with minimal delay. The bypass register is set LOW (V_SS) when the BYPASS
instruction is executed.
3. Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the SRAM. Several balls are
also included in the scan register to reserved balls. The boundary scan register is loaded with the contents of the
SRAM Input and Output ring when the TAP controller is in the capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the shift-DR state. Each bit corresponds to one of the balls on
the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
4. Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE
command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out
when the TAP controller is in the shift-DR state.
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Bit Size
3
1
32
90
TAP Instruction Set
Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP
Instruction Code Table. All other instruction codes that are not listed on this table are reserved and should not be
used. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the
TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the
Update-IR state.
Integrated Silicon Solution, Inc.- www.issi.com
20
Rev. B
10/16/2014