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IS61LPS51236B Datasheet, PDF (6/33 Pages) Integrated Silicon Solution, Inc – Internal self-timed write cycle
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IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
1024K x 18, 119-Ball BGA (Top View)
1
2
A
VDDQ
A
B
NC
A
C
NC
A
D
DQb
NC
E
NC
DQb
F
VDDQ
NC
G
NC
DQb
H
DQb
NC
J
VDDQ
VDD
K
NC
DQb
L
DQb
NC
M
VDDQ
DQb
N
DQb
NC
P
NC
DQPb
R
NC
A
T
NC
A
U
VDDQ
TMS
3
A
A
A
VSS
VSS
VSS
/BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
TDI
4
/ADSP
/ADSC
VDD
NC
/CE
/OE
/ADV
/GW
VDD
CLK
NC
/BWE
A1*
A0*
VDD
NC
TCK
5
A
A
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
TDO
6
A
A
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
7
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
119-Ball, 14 mm x 22 mm BGA
PIN DESCRIPTIONS
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Address Status Processor
/ADSC
Address Status Controller
MODE
Burst Sequence Selection
/CE
Synchronous Chip Enable
/BWE
Byte Write Enable
/BWx (x=a-b)
Synchronous Byte Write Inputs
/GW
Global Write Enable
/OE
Output Enable
DQx
Data Inputs/Outputs
DQPx
TCK,TDI,
TDO,TMS
ZZ
Parity Data I/O
JTAG Pins
Power Sleep Mode
NC
No Connect
VDD
VDDQ
VSS
Power Supply
I/O Power Supply
Ground
Integrated Silicon Solution, Inc.- www.issi.com
6
Rev. B
10/16/2014
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