IS61LPS51236B Datasheet, PDF (12/33 Pages) Integrated Silicon Solution, Inc – Internal self-timed write cycle

IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (Over operating temperature range)
Symbol Parameter
Test Conditions
3.3V
2.5V
Min. Max. Min. Max.
1.8V
Unit
Min.
Max.
Voh
Output Ioh=-4.0 mA(3.3V)
HIGH
Voltage
Ioh=–1.0 mA(2.5V,1.8V)
2.4
—
2.0
—
VDDQ
-0.4
—
V
Vol
Output LOW Iol=8.0 mA(3.3V)
Voltage Iol=1.0 mA(2.5V,1.8V)
—
0.4
—
0.4
—
0.4
V
Vih
Input HIGH
Voltage
2.0
VDD
+0.3
1.7
VDD
+0.3
0.7* VDD
VDD
+0.3
V
Vil
Input LOW
Voltage
–0.3
0.8 –0.3 0.7
–0.3
0.3*
VDD
V
Input
Ili
Leakage Vss≤Vin≤ VDD
–1
1
–1
1
–1
1
μA
Current
Output
Ilo
Leakage Vss≤Vout≤ VDDQ,/OE=Vih
–1
1
–1
1
–1
1
μA
Current
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: Vih (AC) ≤ VDD + 1.5V (Pulse width less than tkc /2)
1.8V: Vih (AC) ≤ VDD + 0.5V (Pulse width less than tkc /2)
3. Undershoot:
3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2)
1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2)
4. MODE pin has an internal pull-up and should be tied to VDD or Vss . It exhibits ±100μA maximum leakage current when tied to ≤Vss+0.2V or ≥ VDD–
0.2V.
5. ZZ pin has an internal pull-down and should be tied to VDD or Vss . It exhibits ±100μA maximum leakage current when tied to ≤Vss+0.2V or ≥ VDD–0.2V.
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Temp.
range
-250
Max
-200
Unit
Max
x18 x36 x18 x36
Icc
AC Operating, Device Selected, OE = Vih, ZZ ≤ Vil,All Inputs ≤ ^{Com. 270 270 220 220}
Supply Current 0.2V or ≥ VDD – 0.2V,Cycle Time ≥ tkc min.
Ind. 290 290 240 240
mA
Isb
Standby
Current TTL
Input
Device Deselected, VDD = Max.,All Inputs ≤ Vil ^{Com. 80 80 70}
or ≥ Vih,ZZ ≤ Vil, f = Max.
Ind. 90 90 80
70
80
mA
Isb1
Standby
Current CMOS
Input
Device Deselected, VDD = Max.,Vin ≤ Vss +
0.2V or ≥ VDD – 0.2V,f = 0
Com. 60 60 60 60
mA
Ind. 70 70 70 70
Note:
1. Power-up assumes a linear ramp from 0V to V_DD (min) within 200ms. During this time Vih < V_DD and V_DDQ < V_DD
Integrated Silicon Solution, Inc.- www.issi.com
12
Rev. B
10/16/2014