IS61LPS51236B Datasheet, PDF (13/33 Pages) Integrated Silicon Solution, Inc – Internal self-timed write cycle

IS61LPS51236B/IS61VPS51236B/IS61VVPS51236B
IS61LPS102418B/IS61VPS102418B/IS61VVPS102418B
CAPACITANCE
Symbol
Parameter
Conditions
Cin
Input Capacitance
Vin = 0V
Cout
Input/Output Capacitance
Vout = 0V
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, VDD = 3.3V.
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Max.
6
8
Unit
pF
pF
Symbol Parameter
-250
Min. Max.
fMAX
Clock Frequency
—
250
tKC
Cycle Time
4
—
tKH
Clock High Time
1.7
—
tKL
Clock Low Time
1.7
—
tKQ
tKQX⁽²⁾
tKQLZ^(2,3)
tKQHZ^(2,3)
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
—
2.6
0.8
—
0.8
—
—
2.6
tOEQ
Output Enable to Output Valid
—
2.6
tOELZ^(2,3) Output Enable to Output Low-Z
0
—
tOEHZ^(2,3) Output Disable to Output High-Z
—
2.6
tAS
Address Setup Time
1.2
—
tWS
Read/Write Setup Time
1.2
—
tCES
Chip Enable Setup Time
1.2
—
tSE
Clock Enable Setup Time
1.2
—
tADVS
Address Advance Setup Time
1.2
—
tDS
Data Setup Time
1.2
—
tAH
Address Hold Time
0.3
—
tHE
Clock Enable Hold Time
0.3
—
tWH
Write Hold Time
0.3
—
tCEH
Chip Enable Hold Time
0.3
—
tADVH
Address Advance Hold Time
0.3
—
tDH
Data Hold Time
0.3
—
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
-200
Min. Max.
—
200
5
—
2
—
2
—
—
3.0
1.5
—
1
—
—
3.0
—
3.0
0
—
—
3.0
1.4
—
1.4
—
1.4
—
1.4
—
1.4
—
1.4
—
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Integrated Silicon Solution, Inc.- www.issi.com
13
Rev. B
10/16/2014