IS61QDPB41M18A Datasheet, PDF (8/33 Pages) Integrated Silicon Solution, Inc – 512Kx36 and 1Mx18 configuration available

IS61QDPB41M18A/A1/A2
IS61QDPB451236A/A1/A2
Sequence3. /Doff is controlled but goes high before clock being stable.
Because DLL has a risk to be locked with the unstable clock, DLL needs to be reset and locked with the stable input.
a) K-stop to reset. If K or K# stays at VIH or VIL for more than 30nS, DLL will be reset and ready to re-lock. In tKC-
Lock period, DLL will be locked with a new stable value. Device can be ready for normal operation after that.
Power On stage Unstable Clock Period
K-Stop
Stable Clock period
Read to use
K
K#
Doff#
VDD
>30nS >tKC-lock for device initialization
VDDQ
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
a) /Doff Low to reset. If /Doff toggled low to high, DLL will be reset and ready to re-lock. In tKC-Lock period, DLL will
be locked with a new stable value. Device can be ready for normal operation after that.
Power On stage Unstable Clock Period Doff reset DLL
Stable Clock period
Read to use
K
K#
Doff#
VDD
>tKC-lock for device
>tDoffLowToReset initialization
VDDQ
VREF
VIN
Note) Applying DLL reset sequences (sequence 3a, 3b) are also required when operating frequency is changed without power off.
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
8
10/02/2014