IS61QDPB41M18A Datasheet, PDF (20/33 Pages) Integrated Silicon Solution, Inc – 512Kx36 and 1Mx18 configuration available

IS61QDPB41M18A/A1/A2
IS61QDPB451236A/A1/A2
Read and Deselect Cycles Timing Diagram
Read
1
tKHKH
2
Read
3
4
K Clock
tKHKL tKLKH
tKHKH
K# Clock
NOP
NOP
NOP
5
6
7
8
9
Address
(SA)
A1
tAVKH tKHAX
A2
R#
tIVKH tKHIX
QVLD
tQVLD
tCHQX1 t_CHQV
tCHQX
tQVLD
tCHQZ
Data-Out
(Q)
2.5 Cycle Read Latency
Q1-0 Q1-1 Q1-2 Q1-3 Q2-0 Q2-1 Q2-2 Q2-3
CQ
tCHCQX
tCHCQV tCQHQV
tCQHQX
CQ#
Undefined
Don’t Care
Notes:
1. Q1-0 , Q1-1, Q1-2, and Q1-3 refer to the output from address A1, Internal burst counter will assign them separately.
2. Outputs are disabled one cycle after NOP.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
20
10/02/2014