IS61QDPB41M18A Datasheet, PDF (7/33 Pages) Integrated Silicon Solution, Inc – 512Kx36 and 1Mx18 configuration available

IS61QDPB41M18A/A1/A2
IS61QDPB451236A/A1/A2
Power-Up and Power-Down Sequences
The recommendation of voltage apply sequence is : V_DD → V_DDQ ¹⁾→V_REF2)→ V_IN
Notes:
V_DDQ can be applied concurrently with V_DD.
V_REF can be applied concurrently with V_DDQ.
After power and clock signals are stabilized, device can be ready for normal operation after tKC-Lock cycles. In tKC-
lock cycle period, device initializes internal logics and locks DLL. Depending on /Doff status, locking DLL will be
skipped. The following timing pictures are possible examples of power up sequence.
Sequence1. /Doff is fixed low
After tKC-lock cycle of stable clock, device is ready for normal operation.
Power On stage Unstable Clock Period
Stable Clock period
Read to use
K
K#
VDD
VDDQ
>tKC-lock for device initialization
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
Sequence2. /Doff is controlled and goes high after clock being stable.
Power On stage
Unstable Clock Period
Stable Clock period
Read to use
K
K#
Doff#
VDD
>tKC-lock for device initialization
VDDQ
VREF
VIN
Note) All inputs including clocks must be either logically High or Low during Power On stage. Timing above shows only one of cases.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
7
10/02/2014