IS61QDPB41M18A Datasheet, PDF (19/33 Pages) Integrated Silicon Solution, Inc – 512Kx36 and 1Mx18 configuration available

IS61QDPB41M18A/A1/A2
IS61QDPB451236A/A1/A2
AC Timing Characteristics
(Over the Operating Temperature Range, V_DD=1.8V±5%, V_DDQ=1.5V/1.8V)
Parameter
Symbol
22 (450MHz)
Min Max
25 (400MHz)
Min Max
Clock
Clock Cycle Time (K, K#)
tKHKH
2.2 8.40 2.50 8.40
Clock Phase Jitter (K, K#)
tKC var
0.15
0.20
Clock High Time (K, K#)
tKHKL
0.4
0.4
Clock Low Time (K, K#)
tKLKH
0.4
0.4
Clock to Clock# (K, K#)
tKHK#H
0.99
1.10
DLL Lock Time (K)
tKC lock
2048
2048
Doff Low period to DLL reset
tDoffLowToReset
5
5
K static to DLL reset
tKCreset
30
30
Output Times
K, K# High to Output Valid
tCHQV
0.45
0.45
K, K# High to Output Hold
tCHQX
-0.45
-0.45
K, K# High to Echo Clock Valid
tCHCQV
0.45
0.45
K, K# High to Echo Clock Hold
tCHCQX
-0.45
-0.45
CQ, CQ# High to Output Valid
tCQHQV
0.2
0.2
CQ, CQ# High to Output Hold
tCQHQX
-0.2
-0.2
K, High to Output High-Z
tCHQZ
0.45
0.45
K, High to Output Low-Z
tCHQX1
-0.45
-0.45
CQ, CQ# High to QVLD Valid
tQVLD
-0.20 0.20 -0.20 0.20
Setup Times
Address valid to K rising edge
tAVKH
0.30
0.40
R#,W# control inputs valid to K
rising edge
tIVKH
0.30
0.40
BW_x# control inputs valid to K rising
edge
tIVKH2
0.25
0.28
Data-in valid to K, K# rising edge
tDVKH
0.25
0.28
Hold Times
K rising edge to address hold
tKHAX
0.30
0.40
K rising edge to R#,W# control
inputs hold
tKHIX
0.30
0.40
K rising edge to BW_x# control inputs
hold
tKHIX2
0.25
0.28
K, K# rising edge to data-in hold
tKHDX
0.25
0.28
30 (333MHz)
Min Max
33 (300MHz)
Min Max
3.00 8.4 3.33 8.4
0.3
0.3
0.4
0.4
0.4
0.4
1.35
1.50
2048
2048
5
5
30
30
0.45
0.45
-0.45
-0.45
0.45
0.45
-0.45
-0.45
0.25
0.27
-0.25
-0.27
0.45
0.45
-0.45
-0.45
-0.25 0.25 -0.27 0.27
0.40
0.40
0.40
0.40
0.30
0.30
0.30
0.30
0.40
0.40
0.40
0.40
0.30
0.30
0.30
0.30
Units Notes
ns
ns
4
cycle
cycle
ns
cycles
5
ns
ns
ns
ns
ns
ns
ns
6
ns
6
ns
ns
ns
ns
ns
2
ns
2
ns
ns
2
ns
2
ns
ns
Notes:
1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R#, W#, BW₀#, BW₁# and (BW₂#, BW₃# for x36)
3. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0 C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70 C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. V_DD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
6. The data sheet parameters reflect tester guard bands and test setup variations.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
19
10/02/2014