IS61QDPB41M18A Datasheet, PDF (12/33 Pages) Integrated Silicon Solution, Inc – 512Kx36 and 1Mx18 configuration available

IS61QDPB41M18A/A1/A2
IS61QDPB451236A/A1/A2
Clock Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Clock Controls
Data In
Mode
K
R# W#
D_B
D_B+1
D_B+2
D_B+3
Q_A
Stop Clock Stop X X
No
Operation L → H H H
(NOP)
Previous
State
X
Read A L → H L X
X
Write B
L→H X L
D_IN at K
(t+2.0)
Previous
State
X
X
D_IN at
K#(t+2.5)
Previous
State
X
X
D_IN at K
(t+3.0)
Previous
State
X
X
D_IN at K#
(t+3.5)
Previous
State
High-Z
D_OUT at
K#(t+2.5)
X
Data Out
Q_A+1
Previous
State
Q_A+2
Previous
State
Q_A+3
Previous
State
High-Z
High-Z
High-Z
D_OUT at K
(t+3.0)
X
D_OUT at K#
(t+3.5)
X
D_OUT at K
(t+4.0)
X
Notes:
1. Internal burst counter is always fixed as four-bit.
2. X = “don’t care”; H = logic “1”; L = logic “0”.
3. A read operation is started when control signal R is active low
4. A write operation is started when control signal W is active low.
5. Before entering into stop clock, all pending read and write commands must be completed.
6. Consecutive read or write operations can be started only at every other K clock rising edge. If two read or write operations are issued in
consecutive K clock rising edges, the second one will be ignored.
7. If both R# and W# are active low after a NOP operation, the write operation will be ignored.
8. For timing definitions, refer to the AC Timing Characteristics table. Signals must meet AC specifications at timings indicated in parenthesis with
respect to switching clocks K and K#.
x18 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
K (t+2.0) K# (t+2.5) K (t+3.0) K# (t+3.5) BW₀#
BW₁#
D_B
Write Byte 0
L→H
L
H
D0-8 (t+2.0)
Write Byte 1
L→H
H
L
D9-17 (t+2.0)
Write All Bytes
L→H
L
L
D0-17 (t+2.0)
Abort Write
L→H
H
H
Don't Care
Write Byte 0
L→H
L
H
Write Byte 1
L→H
H
L
Write All Bytes
L→H
L
L
Abort Write
L→H
H
H
Write Byte 0
L→H
L
H
Write Byte 1
L→H
H
L
Write All Bytes
L→H
L
L
Abort Write
L→H
H
H
Write Byte 0
L→H
L
H
Write Byte 1
L→H
H
L
Write All Bytes
L→H
L
L
Abort Write
L→H
H
H
D_B+1
D0-8 (t+2.5)
D9-17 (t+2.5)
D0-17 (t+2.5)
Don't Care
D_B+2
D0-8 (t+3.0)
D9-17 (t+3.0)
D0-17 (t+3.0)
Don't Care
D_B+3
D0-8 (t+3.5)
D9-17 (t+3.5)
D0-17 (t+3.5)
Don't Care
Notes:
1. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and
K#.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
12
10/02/2014