IS61QDPB41M18A Datasheet, PDF (22/33 Pages) Integrated Silicon Solution, Inc – 512Kx36 and 1Mx18 configuration available

IS61QDPB41M18A/A1/A2
IS61QDPB451236A/A1/A2
Read, Write, and NOP Timing Diagram
Read
Write
Read
Write
NOP
1
tKHKH
2
3
4
5
6
7
8
9
K Clock
tKHKL tKLKH
tKHKH
K# Clock
Address
(SA)
R#
W#
tAVKH tKHAX
A1
A2
A3
A4
tIVKH tKHIX
tIVKH tKHIX
BW_x#
Data-In
(D)
QVLD
Data-Out
(Q)
CQ
B2-1 B2-2 B2-3 B2-4 B4-1 B4-2 B4-3 B4-4
tDVKH
tKHDX
D2-1 D2-2 D2-3 D2-4 D4-1 D4-2 D4-3 D4-4
tQVLD
tQVLD
tCHQV
tCHQX1
2.5 Cycle Read Latency
tCHQV
tCHQX
tCHQZ
tCHQX
Q1-0 Q1-1 Q1-2 Q1-3 Q3-0 Q3-1 Q3-2 Q3-3
tCHCQX
tCHCQV tCQHQV
tCQHQX
CQ＃
Undefined
Don’t Care
Notes:
1. If address A3 = A2, data Q3-0 = D2-0, data Q3-1 = D2-1, data Q3-2 = D2-2, data Q3-3 = D2-3. Write data is forwarded immediately as read
results.
2. B1-0 refers to all BWx# byte controls for D1-0. B1-1, B1-2, and B1-3 refer to all BWx# byte controls for D1-1, D1-2, and D1-3 respectively.
3. B2-0 refers to all BWx# byte controls for D2-0. B2-1, B2-2, and B2-3 refer to all BWx# byte controls for D2-1, D2-2, and D2-3 respectively.
4. Outputs are disabled one cycle after a NOP.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
22
10/02/2014