IS66WVE2M16DBLL Datasheet, PDF (7/28 Pages) Integrated Silicon Solution, Inc – 3.0V Core Async/Page PSRAM

IS66WVE2M16DBLL
Bus Operating Modes
PSRAM products incorporates the industry-standard, asynchronous interface. This bus interface
supports asynchronous Read and WRITE operations as well as page mode READ operation for
enhanced bandwidth. The supported interface is defined by the value loaded into the CR.
Asynchronous Mode Operation
PSRAM products power up in the asynchronous operating mode. This mode uses the industry-
standard SRAM control interface (CE#, OE#, WE#, and LB#/UB#).
READ operations are initiated by bringing CE#, OE#, and LB#/UB# LOW while keeping WE# HIGH
(see Figure 2). Valid data will be driven out of the I/Os after the specified access time has elapsed.
WRITE operations occur when CE#,WE#, and LB#/UB# are driven LOW (see Figure 3). During
WRITE operations, the level of OE# is a “Don’t Care”; WE# overrides OE#. The data to be written is
latched on the rising edge of CE#, WE#, or LB#/UB#, whichever occurs first. WE# LOW time must be
limited to tCEM.
Figure 2. Asynchronous Read Operation
Address
DQ0-
DQ15
CE#
UB#/LB#
OE#
WE#
tRC = READ cycle Time
VALID
ADDRESS
VALID
DATA
Rev.A | May 2012
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