IS66WVE2M16DBLL Datasheet, PDF (19/28 Pages) Integrated Silicon Solution, Inc – 3.0V Core Async/Page PSRAM

IS66WVE2M16DBLL
AC Characteristics
Table 8 . Asynchronous READ Cycle Timing Requirements
Symbol
Parameter
t_AA
Address Acess Time
t_APA
Page access Time
t_BA
LB# /UB# access Time
t_BHZ LB#/UB# disable to High-Z output
t_BLZ LB#/UB# enable to Low-Z output
t_CEM Maximum CE# pulse width
t_CO
Chip select access time
t_HZ
Chip disable to High-Z output
t_LZ
Chip enable to Low-Z output
t_OE
Output enable to valid output
t_OH
Output hold from address change
t_OHZ Output disable to High-Z output
t_OLZ Output enable to Low-Z output
t_PC
Page cycle time
t_RC
Read cycle time
-70
Unit
Min
Max
70
ns
20
ns
70
ns
8
ns
10
ns
8
us
70
ns
8
ns
10
ns
20
ns
5
ns
8
ns
3
ns
20
ns
70
ns
Notes
1
2
3
1
2
1
2
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The High-Z timings
measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The Low-Z timings
measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or VOL.
3. Page mode enable only.
Rev.A | May 2012
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