IS66WVE2M16DBLL Datasheet, PDF (16/28 Pages) Integrated Silicon Solution, Inc – 3.0V Core Async/Page PSRAM

IS66WVE2M16DBLL
Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh
The PAR bits restrict REFRESH operation to a portion of the total memory array. The
refresh options are “full array” and “ none of the array.”
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
The sleep mode bit defines the low-power mode to be entered when ZZ# is driven LOW.
If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is enabled. PAR can
also be enabled directly by writing to the CR using the software-access sequence. Note
that this disables ZZ# initiation of PAR. DPD cannot properly be enabled or disabled
using the software-access sequence; DPD should only be enabled or disabled using ZZ#
to access the CR.
DPD operation disables all refresh-related activity. This mode is used when the system
does not require the storage provided by the PSRAM device. When DPD is enabled, any
stored data will become corrupted. When refresh activity has been re-enabled. The
PSRAM device will require 150us to perform an initialization procedure before normal
operation can resume. DPD should not be enabled using CR software access.
Temperature Compensated Refresh (CR[6:5]) Default = +85^oC Operation
Temperature compensated refresh register bits can be programmed using the CR [5, 6]
configuration registers and has four different temperature levels: +15°C, +45°C, +70°C, and
+85°C. The temperature selected must be equal to or higher than the case temperature of
the device. Setting a lower temperature level would cause data to be corrupted due to
insufficient refresh rate.
Page Mode READ Operation (CR[7]) Default = Disabled
The page mode operation bit determines whether page mode READ operations are enabled
In the power-up default state, page mode is disabled.
Rev.A | May 2012
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