IS66WVE2M16DBLL Datasheet, PDF (12/28 Pages) Integrated Silicon Solution, Inc – 3.0V Core Async/Page PSRAM

IS66WVE2M16DBLL
Configuration Registers Operation
The configuration register (CR) defines how the PSRAM device performs a transparent self refresh.
Altering the refresh parameters can dramatically reduce current consumption during standby mode.
Page mode controls is embedded in the CR. This register can be updated any time the device is
operating in a standby state. The control bits used in the CR are shown in Table 3. At power-up,
the CR is set to 0070h.
Access Using ZZ#
The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGH-to-LOW
transition (see Figure 5). The values placed on addresses A[20:0] are latched into the CR on the
rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t Care.” Access using ZZ#
is WRITE only.
Figure 5: Load Configuration Register Operation Using ZZ#
Address
CE#
WE#
ZZ#
t < 500ns
VALID
ADDRESS
Rev.A | May 2012
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