IS66WVE2M16DBLL Datasheet, PDF (22/28 Pages) Integrated Silicon Solution, Inc – 3.0V Core Async/Page PSRAM

Timing Diagrams
Figure 10: Power-Up Initialization Timing
VDD, VDDQ=2.7V
tPU > 150us
Device Initialization
IS66WVE2M16DBLL
VDD(MIN)
Device ready for
normal operation
Figure 11: Load Configuration Register
t_WC
Address
CE#
OPCODE
t_AW
t_WR
t_CW
UB#/LB#
WE#
t_AS
t_WP
OE#
ZZ#
t_CDZZ
t_ZZWE
Figure 12: DPD Entry and Exit Timing
ZZ#
t_CDZZ
t_ZZ (MIN)
t_R
CE#
Device ready for
normal operation
Rev.A | May 2012
www.issi.com - [e-mail]
22