IS61NP12836 Datasheet, PDF (7/20 Pages) Integrated Silicon Solution, Inc – PIPELINE NO WAIT STATE BUS SRAM

IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ASYNCHRONOUS TRUTH TABLE⁽¹⁾
Operation
ZZ
OE
I/O STATUS
Sleep Mode
Read
Write
Deselected
H
X
L
L
L
H
L
X
L
X
High-Z
DQ
High-Z
Din, High-Z
High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE,
otherwise data bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle
time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
WE
BWa
BWb
READ
H
X
X
WRITE BYTE a
L
L
H
WRITE BYTE b
L
H
L
WRITE ALL BYTEs
L
L
L
WRITE ABORT/NOP
L
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE (x32/x36)
Operation
WE
BWa BWb BWc BWd
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
H
X
X
X
X
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00
ISSI ^®
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