IS61NP12836 Datasheet, PDF (12/20 Pages) Integrated Silicon Solution, Inc – PIPELINE NO WAIT STATE BUS SRAM

IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI ^®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
-150*
Min. Max.
-133
Min. Max.
fmax Clock Frequency
— 150
— 133
tKC
Cycle Time
6.7 —
7.5 —
tKH
Clock High Time
2.5 —
3—
tKL
Clock Low Time
2.5 —
3—
tKQ
Clock Access Time
— 3.8
— 4.2
tKQX⁽²⁾ Clock High to Output Invalid
1.5 —
1.5 —
tKQLZ^(2,3) Clock High to Output Low-Z
0—
0—
tKQHZ^(2,3) Clock High to Output High-Z
—3
— 3.5
tOEQ
Output Enable to Output Valid
— 3.8
— 4.2
tOELZ^(2,3) Output Enable to Output Low-Z
0—
0—
tOEHZ^(2,3) Output Disable to Output High-Z
— 3.5
— 3.5
tAS
Address Setup Time
1.5 —
1.5 —
tWS
Read/Write Setup Time
1.5 —
1.5 —
tCES
Chip Enable Setup Time
1.5 —
1.5 —
tSE
Clock Enable Setup Time
1.5 —
1.5 —
tAVS
Address Advance Setup Time
1.5 —
1.5 —
tDS
Data Setup Time
2.0 —
2.0 —
tAH
Address Hold Time
0.5 —
0.5 —
tHE
Clock EnableHold Time
0.5 —
0.5 —
tWH
Write Hold Time
0.5 —
0.5 —
tCEH
Chip Enable Hold Time
0.5 —
0.5 —
tADVH
Address Advance Hold Time
0.5 —
0.5 —
tDH
Data Hold Time
0.5 —
0.5 —
tPDS
ZZ High to Power Down
—2
—2
tPUS
ZZ Low to Power Down
—2
—2
*This speed available only in NP version
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
-100
Min. Max.
— 100
10 —
3—
3—
—5
1.5 —
0—
— 3.5
—5
0—
— 3.5
1.5 —
1.5 —
1.5 —
1.5 —
1.5 —
2.0 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
0.5 —
—2
—2
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00