IS61NP12836 Datasheet, PDF (14/20 Pages) Integrated Silicon Solution, Inc – PIPELINE NO WAIT STATE BUS SRAM

IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
READ CYCLE TIMING
ISSI ^®
Clock
tADVS tADVH
tKH tKL
tKC
ADV
tAS tAH
A16 - A0 or
A17 - A0
A1
A2
A3
tWS tWH
WE
CKE
tSE tHE
tCES tCEH
CE
OE
Data Out
tOEQ
tOEHZ
Q1-1
tOEHZ
tDS ^tKQ
Q2-1
Q2-2
Q2-3
NOTES: WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Q2-4
Q3-1
Q3-2
Q3-3
tKQHZ
Q3-4
Don't Care
Undefined
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00C
11/30/00