IS61NP12836 Datasheet, PDF (5/20 Pages) Integrated Silicon Solution, Inc – PIPELINE NO WAIT STATE BUS SRAM

IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI ^®
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1
2
3
4
5
6
7
A
VCCQ A6
A4
NC
B
NC
CE2
A3
ADV
C
NC
A7
A2
VCC
D
DQ9
NC
GND
NC
E
NC
DQ10 GND
CE
F
VCCQ NC
GND
OE
G
NC
DQ11 BWb
A17
H
DQ12
NC
GND
WE
J
VCCQ VCC
NC
VCC
K
NC
DQ13 GND CLK
L
DQ14 NC
NC
NC
M
VCCQ DQ15
GND
CKE
N
DQ16 NC
GND
A1
P
NC DQP2 GND
A0
R
NC
A5 MODE VCC
T
NC
A10
A11
NC
U
VCCQ NC
NC
NC
A8
A9
A12
GND
GND
GND
NC
GND
NC
GND
BWa
GND
GND
GND
VCC
A14
NC
A16 VCCQ
CE2
NC
A15
NC
DQP1 NC
NC
DQ8
DQ7 VCCQ
NC
DQ6
DQ5
NC
VCC VCCQ
NC
DQ4
DQ3
NC
NC VCCQ
DQ2
NC
NC
DQ1
A13
NC
NC
ZZ
NC VCCQ
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
VCC
VCC
VCC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
GND
VCCQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A10
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
VCC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
256K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
BWa-BWb
WE
CKE
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQ1-DQ16 Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
DQP1-DQP2 Parity Data I/O DQP1 is parity for
DQ1-8; DQP2 is parity for DQ9-16
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
PRELIMINARY INFORMATION Rev. 00C
11/30/00