IS61NP12836 Datasheet, PDF (3/20 Pages) Integrated Silicon Solution, Inc – PIPELINE NO WAIT STATE BUS SRAM

IS61NP12832 IS61NP12836 IS61NP25618
IS61NLP12832 IS61NLP12836 IS61NLP25618
ISSI ^®
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1
2
3
4
5
6
7
A
VCCQ A6
A4
NC
B
NC
CE2
A3
ADV
C
NC
A7
A2
VCC
D
DQc1
NC
GND
NC
E
DQc2 DQc3 GND
CE
F
VCCQ DQc4 GND
OE
G
DQc5 DQc6 BWc
NC
H
DQc7 DQc8 GND
WE
J
VCCQ VCC
NC
VCC
K
DQd1 DQd2 GND CLK
L
DQd4 DQd3 BWd
NC
M
VCCQ DQd5 GND
CKE
N
DQd6 DQd7 GND
A1
P
DQd8
NC
GND
A0
R
NC
A5 MODE VCC
T
NC
NC
A10 A11
U
VCCQ NC
NC
NC
A8
A9
A12
GND
GND
GND
BWb
GND
NC
GND
BWa
GND
GND
GND
VCC
A14
NC
A16 VCCQ
CE2
NC
A15
NC
NC DQb8
DQb6 DQb7
DQb5 VCCQ
DQb4 DQb3
DQb2 DQb1
VCC VCCQ
DQa7 DQa8
DQa5 DQa6
DQa4 VCCQ
DQa3 DQa2
NC DQa1
A13
NC
NC
ZZ
NC VCCQ
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
VCC
VCC
VCC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
VCC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCCQ
DQa2
DQa1
NC
128K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A16
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
BWa-BWd
WE
CKE
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Write Enable
Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
PRELIMINARY INFORMATION Rev. 00C
11/30/00