IS61NP12836 Datasheet, PDF (1/20 Pages) Integrated Silicon Solution, Inc – PIPELINE NO WAIT STATE BUS SRAM

ISSI ^{IS61NP12832 IS61NP12836 IS61NP25618}
®
IS61NLP12832 IS61NLP12836 IS61NLP25618
128K x 32, 128K x 36 and 256K x 18
PRELIMINARY INFORMATION
PIPELINE 'NO WAIT' STATE BUS SRAM
OCTOBER 2000
FEATURES
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining for TQFP
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119 PBGA package
• Single +3.3V power supply (± 5%)
• NP Version: 3.3V I/O Supply Voltage
• NLP Version: 2.5V I/O Supply Voltage
• Industrial temperature available
DESCRIPTION
The 4 Meg 'NP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
network and communications customers. They are
organized as 131,072 words by 32 bits, 131,072 words
by 36 bits and 262,144 words by 18 bits, fabricated with
ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
*This speed available only in NP version
-150*
-133
3.8
4.2
6.7
7.5
150
133
-100
Units
5
ns
10
ns
100
MHz
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
PRELIMINARY INFORMATION Rev. 00C
11/30/00