IS80LV51 Datasheet, PDF (29/43 Pages) Integrated Silicon Solution, Inc – CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER

IS80LV51
IS80LV31
ISSI ^®
OTHER INFORMATION
Reset
The reset input is the RST pin, which is the input to a
Schmitt Trigger.
A reset is accomplished by holding the RST pin high for at
least two machine cycles (24 oscillator periods), while the
oscillator is running. The CPU responds by generating an
internal reset, with the timing shown in Figure 19.
The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2 of
every machine cycle. The port pins will maintain their
current activities for 19 oscillator periods after a logic 1
has been sampled at the RST pin; that is, for 19 to 31
oscillator periods after the external reset signal has been
applied to the RST pin.
The internal reset algorithm writes 0s to all the SFRs
except the port latches, the Stack Pointer, and SBUF. The
port latches are initialized to FFH, the Stack Pointer to
07H, and SBUF is indeterminate. Table 9 lists the SFRs
and their reset values.
Then internal RAM is not affected by reset. On power-up
the RAM content is indeterminate.
Table 9. Reset Values of the SFR's
SFR Name
PC
ACC
B
PSW
SP
DPTR
P0–P3
IP
IE
TMOD
TCON
TH0
TL0
TH1
TL1
SCON
SBUF
PCON
Reset Value
0000H
00H
00H
00H
07H
0000H
FFH
XXX00000B
0XX00000B
00H
00H
00H
00H
00H
00H
00H
Indeterminate
0XXX0000B
Integrated Silicon Solution, Inc.
29
ADVANCE INFORMATION MC018-0A
10/01/98