IS80LV51 Datasheet, PDF (11/43 Pages) Integrated Silicon Solution, Inc – CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER

IS80LV51
IS80LV31
ISSI ^®
The detail description of each bit is as follows:
PSW:
Program Status Word. Bit Addressable.
7
65
4
3
2
CY AC F0 RS1 RS0 OV
10
—P
Register Description:
CY PSW.7 Carry flag.
AC PSW.6 Auxiliary carry flag.
F0 PSW.5 Flag 0 available to the user for
general purpose.
RS1 PSW.4 Register bank selector bit 1.⁽¹⁾
RS0 PSW.3 Register bank selector bit 0.⁽¹⁾
OV PSW.2 Overflow flag.
— PSW.1 Usable as a general purpose flag
P PSW.0 Parity flag. Set/Clear by hardware each
instruction cycle to indicate an odd/even
number of “1” bits in the accumulator.
Note:
1. The value presented by RS0 and RS1 selects the corresponding
register bank.
RS1 RS0 R00egister Bank Address
0
0
0
00H-07H
0
1
1
08H-0FH
1
0
2
10H-17H
1
1
3
18H-1FH
PCON:
Power Control Register. Not Bit Addressable.
7
65
4
3
2
10
SMOD — — — GF1 GF0 PD IDL
Register Description:
SMOD
—
—
Double baud rate bit. If Timer 1 is used to
generate baud rate and SMOD=1, the baud rate
is doubled when the serial port is used in modes
1, 2, or 3.
Not implemented, reserve for future use.⁽¹⁾
Not implemented, reserve for future use.⁽¹⁾
—
Not implemented, reserve for future use.⁽¹⁾
GF1
General purpose flag bit.
GF0
General purpose flag bit.
PD
Power-down bit. Setting this bit activates power-
down mode.
IDL
Idle mode bit. Setting this bit activates idle
mode. If 1s are written to PD and IDL at the
same time, PD takes precedence.
Note:
1. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION MC018-0A
10/01/98
IE:
Interrupt Enable Register. Bit Addressable.
7
65
4
3
2
10
EA — — ES ET1 EX1 ET0 EX0
Register Description:
EA IE.7
Disable all interrupts. If EA=0, no
interrupt will be acknowledged. If
EA=1, each interrupt source is
individually enabled or disabled by
setting or clearing its enable bit.
— IE.6
Not implemented, reserve for future
use.⁽⁵⁾
— IE.5
Not implemented, reserve for future
use.⁽⁵⁾
ES IE.4
Enable or disable the serial port
interrupt.
ET1 IE.3
Enable or disable the timer 1 overflow
interrupt.
EX1 IE.2
Enable or disable external interrupt 1.
ET0 IE.1
Enable or disable the timer 0 overflow
interrupt.
EX0 IE.0
Enable or disable external interrupt 0.
Note:
To use any of the interrupts in the 80C51 Family, the follow-
ing three steps must be taken:
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the coresponding individual interrupt enable bit in
the IE register to 1.
3. Begin the interrupt service routine at the corresponding
Vector Address of that interrupt (see below).
Interrupt Source
IE0
Vector Address
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI & TI
0023H
4. In addition, for external interrupts, pins INT0 and INT1
(P3.2 and P3.3) must be set to 1, and depending on
whether the interrupt is to be level or transition activated,
bits IT0 or IT1 in the TCON register may need to be set to
0 or 1.
ITX = 0 level activated (X = 0, 1)
ITX = 1 transition activated
5. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
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