IS80LV51 Datasheet, PDF (28/43 Pages) Integrated Silicon Solution, Inc – CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER

IS80LV51
IS80LV31
Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at least
12 oscillator periods to ensure sampling. If the external
interrupt is transition-activated, the external source has to
hold the request pin high for at least one machine cycle,
and then hold it low for at least one machine cycle to
ensure that the transition is seen so that interrupt request
flag IEx will be set. IEx will be automatically cleared by the
CPU when the service routine is called.
If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then the external source
must deactivate the request before the interrupt service
routine is completed, or else another interrupt will be
generated.
Response Time
The INT0 and INT1 levels are inverted and latched into the
interrupt flags IE0 and IE1 at S5P2 of every machine
cycle. Similarly, the Serial Port flags RI and TI are set at
S5P2. The values are not actually polled by the circuitry
until the next machine cycle.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle.
If a request is active and conditions are right for it to be
acknowledged, a hardware subroutine call to the requested
service routine will be the next instruction executed. The
call itself takes two cycles. Thus, a minimum of three
complete machine cycles elapsed between activation of
an external interrupt request and the beginning of execution
of the first instruction of the service routine. Figure 17
shows response timings.
A longer response time results if the request is blocked by
one of the three previously listed conditions. If an interrupt
of equal or higher priority level is already in progress, the
additional wait time depends on the nature of the other
interrupt's service routine. If the instruction in progress is
not in its final cycle, the additional wait time cannot be
more than three cycles, since the longest instructions
(MUL and DIV) are only four cycles long. If the instruction
in progress is RETI or an access to IE or IP, the additional
wait time cannot be more than five cycles (a maximum of
one more cycle to complete the instruction in progress,
plus four cycles to complete the next instruction if the
instruction is MUL or DIV).
Thus, in a single-interrupt system, the response time is
always more than three cycles and less than nine cycles.
ISSI ^®
Single-Step Operation
The IS80LV51/31 interrupt structure allows single-step
execution with very little software overhead. As previously
noted, an interrupt request will not be serviced while an
interrupt of equal priority level is still in progress, nor will
it be serviced after RETI until at least one other instruction
has been executed. Thus, once an interrupt routine has
been entered, it cannot be reentered until at least one
instruction of the interrupted program is executed. One
way to use this feature for single-step operation is to
program one of the external interrupts (for example, INT0)
to be level-activated. The service routine for the interrupt
will terminate with the following code:
JNB P3.2,$ ;Wait Here Till INT0 Goes High
JB
P3.2,$ ;Now Wait Here Till it Goes Low
RETI
;Go Back and Execute One
Instruction
If the INT0 pin, which is also the P3.2 pin, is held normally
low, the CPU will go right into the External Interrupt 0
routine and stay there until INT0 is pulsed (from low-to-
high-to-low). Then it will execute RETI, go back to the task
program, execute one instruction, and immediately reenter
the External Interrupt 0 routine to await the next pulsing of
P3.2. One step of the task program is executed each time
P3.2 is pulsed.
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Integrated Silicon Solution, Inc.
ADVANCE INFORMATION MC018-0A
10/01/98