IS80LV51 Datasheet, PDF (25/43 Pages) Integrated Silicon Solution, Inc – CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER

IS80LV51
IS80LV31
ISSI ^®
INTERRUPT SYSTEM
The IS80LV51/31 provides sic interrupt sources: two
external interrupts, three timer interrupts, and a serial port
interrupt. These are shown in Figure 16.
The External Interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits
IT0 and IT1 in Register TCON. The flags that actually
generate these interrupts are the IE0 and IE1 bits in
TCON. When the service routine is vectored to, hardware
clears the flag that generated an external interrupt only if
the interrupt was transition-activated. If the interrupt was
level-activated, then the external requesting source (rather
than the on-chip hardware) controls the request flag.
The Timer 0 and Timer 1 Interrupts are generated by TF0
and TF1, which are set by a rollover in their respective
Timer/Counter registers (except for Timer 0 in Mode 3).
When a timer interrupt is generated, the on-chip hardware
clears the flag that generated it when the service routine
is vectored to.
The Serial Port Interrupt is generated by the logical OR of
RI and TI. Neither of these flags is cleared by hardware
when the service routine is vectored to. In fact, the service
routine normally must determine whether RI or TI generated
the interrupt, and the bit must be cleared in software.
All of the bits that generate interrupts can be set or cleared
by software, with the same result as though they had been
set or cleared by hardware. That is, interrupts can be
generated and pending interrupts can be canceled in
software.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE (interrupt enable) at address 0A8H. As well as
individual enable bits for each interrupt source, there is a
global enable/disable bit that is cleared to disable all
interrupts or set to turn on interrupts (see SFR IE).
INT0
TCON.1
IE.0
IE.7
IP.0
EXTERNAL
INT RQST 0
IE0
EX0
PX0
TCON.5
IE.1
IP.1
TIMER/COUNTER 0
TF0
ET0
PT0
TCON.3
IE.2
IP.2
INT1
EXTERNAL
INT RQST 1
IE1
EX1
PX1
TCON.7
IE.3
IP.3
TIMER/COUNTER 1
TF1
ET1
PT1
INTERNAL ^SCON.0
IE.4
IP.4
SERIAL
RI
PORT ^SCON.1
TI
ES
EA
PS
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION MC018-0A
10/01/98
Figure 16. Interrupt System
POLLING
HARDWARE
HIGH PRIORITY
INTERRUPT
REQUEST
SOURCE
I.D.
VECTOR
LOW PRIORITY
INTERRUPT
REQUEST
SOURCE
I.D.
VECTOR
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