IS80LV51 Datasheet, PDF (27/43 Pages) Integrated Silicon Solution, Inc – CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER

IS80LV51
IS80LV31
ISSI ^®
Thus, the processor acknowledges an interrupt request
by executing a hardware-generated LCALL to the
appropriate servicing routine. In some cases it also clears
the flag that generated the interrupt, and in other cases it
does not. It never clears the Serial Port flag. This must be
done in the user's software. The processor clears an
external interrupt flag (IE0 or IE1) only if it was transition-
activated. The hardware-generated LCALL pushes the
contents of the Program Counter onto the stack (but it
does not save the PSW) and reloads the PC with an
address that depends on the source of the interrupt being
serviced, as follows:
Interrupt Interrupt
Source Request Bits
INT0
IE0
Timer 0
TF0
INT1
IE1
Timer 1
Serial Port
System
Reset
TF1
RI, TI
RST
Cleared by
Hardware
No (level)
Yes (trans.)
Yes
No (level)
Yes (trans.)
Yes
No
Vector
Address
0003H
000BH
0013H
001BH
0023H
0000H
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted
program continues from where it left off.
Note that a simple RET instruction would also have
returned execution to the interrupted program, but it
would have left the interrupt control system thinking an
interrupt was still in progress.
Interrupt
External 0
External 1
Timer 1
Timer 0
Serial Port
Serial Port
Flag
IE0
IE1
TF1
TF0
TI
RI
SFR Register and
Bit Position
TCON.1
TCON.3
TCON.7
TCON.5
SCON.1
SCON.0
When an interrupt is accepted the following action occurs:
1. The current instruction completes operation.
2. The PC is saved on the stack.
3. The current interrupt status is saved internally.
4. Interrupts are blocked at the level of the interrupts.
5. The PC is loaded with the vector address of the ISR
(interrupts service routine).
6. The ISR executes.
The ISR executes and takes action in response to the
interrupt. The ISR finishes with RETI (return from interrupt)
instruction. This retrieves the old value of the PC from the
stack and restores the old interrupt status. Execution of
the main program continues where it left off.
External Interrupts
The external sources can be programmed to be level-
activated or transition-activated by setting or clearing bit
IT1 or IT0 in Register TCON. If ITx= 0, external interrupt
x is triggered by a detected low at the INTx pin. If ITx = 1,
external interrupt x is edge-triggered. In this mode if
successive samples of the INTx pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEx
in TCON is set. Flag bit IEx then requests the interrupt.
Integrated Silicon Solution, Inc.
27
ADVANCE INFORMATION MC018-0A
10/01/98