X5643 Datasheet, PDF (9/19 Pages) Intersil Corporation – CPU Supervisor with 64Kbit SPI EEPROM

X5643, X5645
Figure 8. Write Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
SI
16 Bit Address
Data Byte 1
15 14 13
3 2 107 65 43 2 10
CS
SCK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Data Byte N
654 321 0
Figure 9. Status Register Write Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
Data Byte
7 6 5 43 2 1 0
SO
High Impedance
SYMBOL TABLE
WAVEFORM INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
9
FN8135.1
July 18, 2005