X5643 Datasheet, PDF (8/19 Pages) Intersil Corporation – CPU Supervisor with 64Kbit SPI EEPROM

X5643, X5645
While the write is in progress following a status register or
EEPROM sequence, the status register may be read to
check the WIP bit. During this time the WIP bit will be high.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
Figure 6. Read Status Register Sequence
CS
– The write enable latch is reset.
– The flag bit is reset.
– Reset signal is active for t_PURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the write
enable latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Instruction
SI
SO
High Impedance
Data Out
76543210
MSB
Figure 7. Write Enable Latch Sequence
CS
SCK
01234567
SI
High Impedance
SO
8
FN8135.1
July 18, 2005