X5643 Datasheet, PDF(6/19 Page) Intersil Corporation – CPU Supervisor with 64Kbit SPI EEPROM

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X5643 Datasheet, PDF (6/19 Pages) Intersil Corporation – CPU Supervisor with 64Kbit SPI EEPROM

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X5643, X5645

Table 2. Block Protect Matrix

WREN CMD Status Register Device Pin

Block

WEL

WPEN

WP#

Protected Block

Protected

Unprotected Block

Protected

Writable

Status Register

WPEN, BL0, BL1

WD0, WD1

Protected

Writable

The Write Enable Latch (WEL) bit indicates the sta-

tus of the write enable latch. When WEL = 1, the

latch is set HIGH and when WEL = 0 the latch is reset

LOW. The WEL bit is a volatile, read only bit. It can

be set by the WREN instruction and can be reset by

the WRDS instruction.

The block lock bits, BL0 and BL1, set the level of block

lock protection. These nonvolatile bits are pro-

grammed using the WRSR instruction and allow the

user to protect one quarter, one half, all or none of the

EEPROM array. Any portion of the array that is block

lock protected can be read but not written. It will

remain protected until the BL bits are altered to disable

block lock protection of that portion of memory.

Status

BL1 BL0

Array Addresses Protected

X5643/X5645

None

$1800-$1FFF

$1000-$1FFF

$0000-$1FFF

The watchdog timer bits, WD0 and WD1, select the

watchdog time out period. These nonvolatile bits are

programmed with the WRSR instruction.

Status Register Bits

WD1

WD0

Watchdog Time Out

(Typical)

1.4 seconds

600 milliseconds

200 milliseconds

disabled

The FLAG bit shows the status of a volatile latch that

can be set and reset by the system using the SFLB

and RFLB instructions. The flag bit is automatically

reset upon power-up. This flag can be used by the sys-

tem to determine whether a reset occurs as a result of

a watchdog time out or power failure.

The nonvolatile WPEN bit is programmed using the

WRSR instruction. This bit works in conjunction with the

WP pin to provide an in-circuit programmable ROM func-

tion (Table 2). WP is LOW and WPEN bit programmed

HIGH disables all status register write operations.

In Circuit Programmable ROM Mode

This mechanism protects the block lock and watchdog

bits from inadvertent corruption.

In the locked state (programmable ROM mode) the WP pin

is LOW and the nonvolatile bit WPEN is â1â. This mode

disables nonvolatile writes to the deviceâs status register.

FN8135.1

July 18, 2005

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