X5643 Datasheet, PDF (2/19 Pages) Intersil Corporation – CPU Supervisor with 64Kbit SPI EEPROM

PIN CONFIGURATION
CS/WDI
SO
WP
V_SS
8-Lead PDIP
1
8
2
7
3 ^X5643/45 6
4
5
X5643, X5645
V_CC
RESET/RESET
SCK
SI
NC
CS/WDI
CS/WDI
SO
WP
V_SS
NC
14-Lead SOIC
1
14
2
13
3
12
4 ^X5643/45 11
5
10
6
9
7
8
NC
V_CC
V_CC
RESET/RESET
SCK
SI
NC
Pin
PDIP
1
2
5
6
3
4
8
7
Pin
SOIC
2&3
Pin
TSSOP
2
4
3
9
13
10
14
5
7
6
8
12 & 13 19
11
18
1, 7, 8, 1, 4-6,
14
9-12,
15-17, 20
Name
CS/WDI
SO
SI
SCK
WP
V_SS
V_CC
RESET/
RESET
NC
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the de-
vice will be in the standby power mode. CS LOW enables the device, placing it
in the active power mode. Prior to the start of any operation after power-up, a
HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog
timer. The absence of a HIGH to LOW transition within the watchdog time out
period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock. The serial clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever V_CC falls below the minimum V_CC sense level. It
will remain active until V_CC rises above the minimum V_CC sense level for
200ms. RESET/RESET goes active if the watchdog timer is enabled and CS
remains either HIGH or LOW longer than the selectable watchdog time out pe-
riod. A falling edge of CS will reset the watchdog timer. RESET/RESET goes
active on power-up at about 1V and remains active for 200ms after the power
supply stabilizes.
No internal connections
2
FN8135.1
July 18, 2005