X5643 Datasheet, PDF (1/19 Pages) Intersil Corporation – CPU Supervisor with 64Kbit SPI EEPROM

®
Data Sheet
X5643, X5645
(Replaces X25643, X25645)
July 18, 2005
FN8135.1
CPU Supervisor with 64Kbit SPI EEPROM
FEATURES
• Selectable watchdog timer
• Low V_CC detection and reset assertion
—Five standard reset threshold voltages
—Re-program low V_CC reset threshold voltage
using special programming sequence
—Reset signal valid to V_CC = 1V
• Determine watchdog or low voltage reset with a
volatile flag bit
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
Block Lock^™ protection
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—8-lead PDIP, 14-lead SOIC
DESCRIPTION
These devices combine four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Block Lock Protect Serial EEPROM
Memory in one package. This combination lowers sys-
tem cost, reduces board space requirements, and
increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcon-
troller fails to restart a timer within a selectable time out
interval, the device activates the RESET/RESET signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even after
cycling the power.
The device’s low V_CC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when V_CC falls below the minimum V_CC
trip point. RESET/RESET is asserted until V_CC returns
to proper operating level and stabilizes. Five industry
standard V_TRIP thresholds are available, however,
Intersil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
BLOCK DIAGRAM
WP
SI
SO
SCK
CS/WDI
Watchdog Transition
Detector
Protect Logic
Data
Register
Command
Decode &
Control
Logic
Status
Register
16Kbits
16Kbits
V_CC Threshold
Reset logic
32Kbits
V_CC
+
V_TRIP
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET/RESET
X5643 = RESET
X5645 = RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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