X5001_06 Datasheet, PDF (9/20 Pages) Intersil Corporation – CPU Supervisor

Figure 5. Read Watchdog Timer Setting
CS
X5001
01234567
SCK
...
RWDT
Instruction
SI
...
SO
WW
DD
...
10
Figure 6. Enable Watchdog Change/Disable Watchdog Change Sequence
CS
SCK
SI
01234567
Instruction
(1 Byte)
High Impedance
SO
Figure 7. Write Watchdog Timer Sequence
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
SO
High Impedance
Data Byte
6 54 3
WW
DD
10
9
FN8125.1
May 30, 2006