X5001_06 Datasheet, PDF (1/20 Pages) Intersil Corporation – CPU Supervisor

®
Data Sheet
May 30, 2006
X5001
FN8125.1
CPU Supervisor
FEATURES
• 200ms power-on reset delay
• Low V_CC detection and reset assertion
—Five standard reset threshold voltages
—Adjust low V_CC reset threshold voltage using
special programming sequence
—Reset signal valid to V_CC = 1V
• Selectable nonvolatile watchdog timer
—0.2, 0.6, 1.4 seconds
—Off selection
—Select settings through software
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
• 2.7V to 5.5V operation
• SPI mode 0 interface
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Watchdog change latch
• High reliability
• Available packages
—8 Ld TSSOP
—8 Ld SOIC
—8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
SI
SO
SCK
CS/WDI
Data
Register
Command
Decode &
Control
Logic
Watchdog
Transition
Detector
V_CC
+
V_TRIP
-
DESCRIPTION
This device combines three popular functions, Power-
on Reset, Watchdog Timer, and Supply Voltage
Supervision in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
The watchdog timer provides an independent protec-
tion mechanism for microcontrollers. During a system
failure, the device will respond with a RESET signal
after a selectable time out interval. The user selects the
interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low V_CC detection circuitry. When
V_CC falls below the minimum V_CC trip point, the system
is reset. RESET is asserted until V_CC returns to proper
operating levels and stabilizes. Five industry standard
V_TRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
The device utilizes Intersil’s proprietary Direct Write^™
cell for the watchdog timer control bits and the V_TRIP
storage element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
Watchdog
Timer
Reset &
Watchdog
Timebase
Power-on/
Low Voltage
REset
Generation
RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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