X5001_06 Datasheet, PDF (7/20 Pages) Intersil Corporation – CPU Supervisor

Figure 4. V_TRIP Programming Sequence
X5001
V_TRIP Programming
Execute
Reset V_TRIP
Sequence
Set V_CC = V_CC Applied =
Desired V_TRIP
New V_CC Applied =
Old V_CC Applied + Error
Execute
Set V_TRIP
Sequence
Apply 5V to V_CC
Decrement V_CC
(V_CC = V_CC - 50mV)
New V_CC Applied =
Old V_CC Applied - Error
Execute
Reset V_TRIP
Sequence
NO
Error < 0
RESET pin
goes active?
YES
Measured V_TRIP -
Desired V_TRIP
Error > 0
Error = 0
DONE
SPI INTERFACE
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device monitors the CS/WDI line and asserts
RESET output if there is no activity within user select-
able timeout period. The device also monitors the V_CC
supply and asserts the RESET if V_CC falls below a
preset minimum (V_TRIP). The device contains an 8-bit
watchdog timer register to control the watchdog time
out period. The current settings are accessed via the
SI and SO pins.
All instructions (Table 1) and data are transferred MSB
first. Data input on the SI line is latched on the first ris-
ing edge of SCK after CS goes LOW. Data is output
on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start
it again to resume operations where left off.
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FN8125.1
May 30, 2006