X5001_06 Datasheet, PDF (13/20 Pages) Intersil Corporation – CPU Supervisor

X5001
Data Output Timing
Symbol
f_SCK
t_DIS
t_V
t_HO
t_RO(3)
t_FO(3)
Parameter
Clock frequency
Output disable time
Output valid from clock low
Output hold time
Output rise time
Output fall time
1.8V-3.6V
Min.
Max.
0
1
400
400
0
300
300
2.7V-5.5V
Min.
Max.
0
2
200
200
0
150
150
Unit
MHz
ns
ns
ns
ns
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t_WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Figure 10. Data Output Timing
CS
SCK
t_CYC
t_WH
t_LAG
t_V
t_HO
t_WL
t_DIS
SO
MSB Out
MSB–1 Out
LSB Out
SI
ADDR
LSB IN
Figure 11. Data Input Timing
CS
SCK
SI
t_LEAD
t_SU
t_H
MSB In
SO
High Impedance
t_CS
t_LAG
t_RI
t_FI
LSB In
13
FN8125.1
May 30, 2006