ISL6211 Datasheet, PDF (9/16 Pages) Intersil Corporation – Crusoe™ Processor Core-Voltage Regulator

ISL6211
R3 = -_V----_R----_E----_F-----–----^VV----^DD----^SS----^XX-----^•_+-----^RR----¹-₁-----_•----₁----₀---_µ----_A---
Output Voltage Droop
An output voltage ’droop’ or an active voltage positioning is
now widely used in the computer power applications. The
technique is based on raising the converter voltage at light
load in anticipation of a possible load current step, Figure 4.
Conversely, the output voltage is lowered at high load in
anticipation of possible load drop. The output voltage varies
with the load as if a resistor were connected in series with
the converter’s output. When done as a part of the feedback
in a closed loop, the droop is not associated with substantial
power losses, though, because there is no such resistor in
the real circuit, rather the feature is emulated through
feedback.
V_CPU
1.2V
VID CODE PROGRAMMED VOLTAGE
LOAD LINE
V_DROOP
0
I_{MAX ICPU}
FIGURE 4. OUTPUT VOLTAGE DROOP
To get the most from the droop, its value should be scaled
with capacitor’s ESR voltage drop.
V_DROOP = I_MAX • ESR
As Figure 5 shows, droop allows reduced size and cost of
the output capacitors required to handle CPU current
transients.
I_o
a)
V_ESR NO DROOP
b)
V_ESR ~ V_DROOP
The Crusoe processor regulation window including
transients is specified as +5%...-2%. To accommodate the
droop, the output voltage of the converter is raised ~3.5% at
no load conditions as it is shown in the Figure 6.
ISL6211
VSEN ¹⁶
V_OUT
R1
R2
Vrise,% = R1/(R1+R2)
FIGURE 6. SETTING THE OUTPUT VOLATGE RISE AT NO
LOAD CONDITIONS
The value of the resistor connected between the ISEN pin
and the drain of the lower MOSFET sets the droop value.;
R_CS
=
2_----0_---8_----3_----•_-----I_{--M----A----X-----}•_-----R_{----D----S----(--O-----N----) – 100Ω}
V_DROOP
Where, V_DROOP is a desired value of the droop at maximum
CPU current, I_MAX is a peak value of the inductor current in
maximum load, R_DS(ON) is a lower MOSFET impedance in
conducting state.
The converter response to a load step is shown in the Figure
7. At zero load current, the output voltage is raised ~50mV
above nominal value of 1.35V. When the load current
increases, the output voltage droops down approximately
55mV. Due to use of droop, the converter’s output voltage
adoptively changes with the load current allowing better
utilization of the regulation window.
UPPER LIMIT
V_CPU = 1.35V
1
LOWER LIMIT
c)
FIGURE 5. ADAPTIVE VOLTAGE POSITIONING
The reduction may be almost two times when compared to a
system without the droop. Additionally, the CPU power
dissipation is also slightly reduced as it is proportional to the
applied voltage squared and even slight voltage decrease
translates in a measurable reduction in power dissipated.
9
I_CPU = 0A...5.0A
2
CH1 50mV
CH2 2.0A
M50µs
FIGURE 7. CONVERTER RESPONSE TO LOAD STEP
Operation Mode Control