ISL6211 Datasheet, PDF (5/16 Pages) Intersil Corporation – Crusoe™ Processor Core-Voltage Regulator

Block Diagram
FREQ
VIN
CLK / RAMP
EN VCC GND
POWER-ON
RESET (POR)
OC LOGIC
PWM VCC
LATCH
QD
R
Q<
-
OVP
UVO
OUTPUT
VOLTAGE
MONITOR
VSEN
OC COMP
-
1.24V
+
-
PGOOD
OCSET
HI
OFF
GATE LOGIC
FCCM
DEADT
PWM/HYST
PWM ON
HYST ON
LO
HGDR
GATE
CONTROL
VCC
LGDR1
OVP1
HYST COMP1
-
DAC OUT
BOOT
UGATE
PHASE
LGATE
PGND
EA1
-
Σ
VSEN
MODE
CONTROL PHASE
LOGIC
-
+ ^{MODE CHANGE COMP}
LGATE
LGATE
-
ISEN
VCC
FCCM
DAC
REFERENCE
SOFT START
10µA
FCCM
VID0 VID2 VID4 SOFT
VID1 VID3
ALTV