ISL6211 Datasheet, PDF (7/16 Pages) Intersil Corporation – Crusoe™ Processor Core-Voltage Regulator

ISL6211
Description
Operation Overview
The ISL6211 is a single output power management integrated
circuit to address power needs of modern processors for
notebook and sub-notebook PCs. The IC controls operation of
a synchronous buck converter. The output voltage can be
adjusted in the range from 0.6V to 1.75V by changing the
DAC code settings (see Table 1). Alternatively, the output
voltage can be set by an analog input. This feature is
important in systems where VID code may not be determined
during start-up or CPU core power saving modes. The output
voltage of the core converter can be changed on-the-fly with
programmable slew rate, which makes it especially suitable
for Crusoe processors.
The converter can operate in two modes: fixed frequency
PWM and variable frequency hysteretic depending on the
load level. At loads lower than the critical where filter
inductor current becomes discontinuous, hysteretic mode of
operation is activated. Switchover from PWM to hysteretic
operation at light loads improves the converters' efficiency
and prolongs battery run time. As the filter inductor resumes
continuous current, the PWM mode of operation is restored.
The hysteretic mode of operation can be omitted by
connecting the FCCM pin to GND.
The core converter incorporates Intersil's proprietary output
voltage droop for optimum handling of fast load transients
found in modern processors.
Initialization
The IPM6211 initializes upon receipt of input power
assuming EN is high. The Power-On Reset (POR) function
continually monitors the input supply voltage on the VCC pin
and initiates soft-start operation after input supply voltage
exceeds 4.6V. Should this voltage drop lower than 4.2V,
POR disables the chip.
Soft-Start
When soft start is initiated, the voltage on the SOFT pin
starts to ramp gradually due to the 25µA current sourced into
the external capacitor.
When SOFT-pin voltage reaches 0.5V, the value of the
sourcing current rapidly changes to 500µA charging the soft-
start capacitor to the level determined by the DAC. This
completes the soft start sequence, Figure 2. As long as the
SOFT voltage is above 0.5V, the maximum value of the internal
soft-start current is set to 500µA allowing fast rate-of-change in
the core output voltage due to a VID code change. In this mode
SOFT has both sourcing and sinking capabilities to maintain
voltage across the soft-start capacitor conforming to the VID
code.
This dual slope approach helps to provide safe rise of
voltages and currents in the converters during initial start-up
and at the same time sets a controlled speed of the core
voltage change when the processor commands to do so.
EN
2
SOFT
1
VOUT
3
4
PGOOD
CH1 500mV
CH3
CH2 5.0V
CH4 5.0V
FIGURE 1.
M 5.00ms
The value of the soft-start capacitor can be estimated by the
following equation:
Csoft
=
-^∆----^I--^s----^s---^m----
∆Vdac
∆
t
For the typical conditions when Vdac=0.05V, Dt=32µs
Csoft
=
5_----0_---0_----µ_----A_--
0.05 V
32 µ
s=
0.33 µ F
With this value of the soft-start capacitor, soft start time will
be equal to:
Tsoft = -⁰---^.--³---³---₂-^µ--₅--^F--_µ---^â‹-_A--⁰---^.--⁵----^V-- = 6.6ms
The ramp up time to 1.2V will be equal to:
Tup = 6.6 + 0.46 = 7.06ms
Converter Operation
At the nominal current core converter operates in a fixed
frequency PWM mode. The output voltage is compared with
a reference voltage set by the DAC. The derived error signal
is amplified by an internally compensated error amplifier and
applied to the inverting input of the PWM comparator. To
provide output voltage droop for enhanced dynamic load
regulation, a signal proportional to the output current is
added to the voltage feedback signal. This feedback scheme
in conjunction with a PWM ramp proportional to the input
voltage allows for fast and stable loop response over a wide
range of input voltage and output current variations. For the
sake of efficiency and maximum simplicity, the current sense
signal is derived from the voltage drop across the lower
MOSFET during its conduction time.
Output Voltage Program
The output voltage of the converter is programmed to discrete
levels between 0.6V_DC and 1.75V_DC as specified in Table 1.
This output is designed to supply the microprocessor core
voltage. The voltage identification (VID) pins program an
internal voltage reference (DAC) through a TTL-compatible
5-bit digital-to-analog converter. The level of the DAC voltage
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