ISL6211 Datasheet, PDF (6/16 Pages) Intersil Corporation – Crusoe™ Processor Core-Voltage Regulator

ISL6211
Functional Pin Description (Pins are
referenced to SSOP package)
GND (Pin 1)
This is a signal ground for the IC. All voltage levels are
measured with respect to this pin.
VCC (Pin 2)
This pin powers the chip. The IC starts to operate when
voltage on this pin exceeds 4.6V and shuts down when it
drops below 4.2V.
PGOOD (Pin 3)
PGOOD is an open drain output used to indicate the status
of the output voltage. This pin is pulled low when the core
output is not within +25% -10% of the VID reference voltage,
or when any of the fault conditions have occurred. The
PGOOD signal is kept asserted high during LongRun™
transitions.
EN (Pin 4)
This pin enables IC operation when left open or pulled-up to
VCC. Also, it unlatches the chip after fault if being cycled.
FCCM (Pin 5)
This pin inhibits hysteretic mode of operation when set low.
ALTV (Pin 6)
Alternatively to VID code programming, the output voltage
can be set by this pin. Such a requirement may occur during
CPU initialization or during some power saving modes.
FREQ (Pin 7)
This pin sets the controller switching frequency. When
connected to ground, the frequency is set to 300kHz. For
600kHz operation pin shall be connected to VCC.
VID0, VID1, VID2, VID3, VID4 (Pins 12, 11, 10, 9 and
8 respectively)
VID0-VID4 are the input pins to the 5-bit DAC. These five
pins program the internal voltage reference, which sets the
converter output voltage. It also sets the core PGOOD, UVP
and OVP thresholds.
VIN (Pin 13)
VIN provides battery voltage to the oscillator for feed-forward
rejection of input voltage variations.
SOFT (Pin 14)
This pin programs the soft start time during initialization and
slew rate of core voltage during VID code change. Connect a
capacitor from this pin to the ground. This capacitor (typically
0.2µF), along with an internal 25µA current source, sets the
soft-start interval of the converter. When voltage on this pin
exceeds 0.5V, the soft start is completed. After the soft-start
is completed, the pin function has changed. The internal
circuit regulates voltage on this pin to the value commanded
by VID code. The pin now has 500µA source/sink capability
that allows to set desired slew rate for upward and
downward VID code changes.
OCSET (Pin 15)
A resistor from this pin to the ground sets the over-current
protection level.
VSEN (Pins 16)
This pin provides sensing of CPU core voltage. The
PGOOD, UVP and OVP comparators use voltage sensed by
this pin for protection and monitoring.
BOOT (Pin 18)
This pin supplies power to the upper MOSFET driver.
Connect this pin to the junction of the bootstrap capacitor
and the cathode of the bootstrap diode. The anode of the
bootstrap diode is are connected to pin 24, PVCC.
UGATE (Pin 19)
This pin provides gate drive to the upper MOSFET.
PHASE (Pin 20)
The PHASE node is a junction point of the upper MOSFET
source, output filter inductor, and lower MOSFET drain.
ISEN (Pin 21)
This pin monitors the voltage drop across the lower
MOSFET for current feedback and output voltage droop. To
set the gain of the current sense amplifier, a resistor should
be placed in series with ISEN input. For precise current
detection, the optional current sense resistor placed in series
with the source of the lower MOSFET can be used.
PGND (Pin 22)
This pin serves as a return path for the lower MOSFET gate
driver. Tie the lower MOSFET source to this pin.
LGATE (Pin 23)
This pin provides gate drive to the lower MOSFET.
PVCC (Pin 24)
This pin powers the lower MOSFET gate driver.
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